Mr. PUNIT LATHIYA

Faculty Details


  • Designation : Assistant Professor
  • Qualification : M.E. E.C. - Signal Processing and VLSI Technology
  • Experience : 4 Years
  • Area Of Interest : Embedded System, VLSI Design, Image Processing

Educational Qualification

  • M.E.E.C. (Signal Processing and VLSI Technology) : Gold Medalist : Year of Completion 2012
  • B.E. Electronics and Communication. : Year of Passing 2007

Work Experience

  1. As a ASIC Engineer @ eInfochips LTD, Ahmedabad (April-2008 to April-2009)
  2. As a Lecturer @ VVP Engineering College, Rajkot (July-2009 to Sep-2010)
  3. As a Assistant Professor @ RK University, Rajkot (June-2012 to May-2017)                                                     

Skills and Knowledge

Having skills in
  1. VLSI Front End Design
  2. Embedded System
  3. Image Processing

Course Taught

During span of 7+ year of Academic carrier taught many subjects like:
  1. Digital Electronics
  2. Analog Electronics
  3. Microprocessor (8085) and Interfacing
  4. Microcontroller (8051,AVR) and Interfacing
  5. Embedded System
  6. VLSI Technology and Design
  7. ASIC Design
  8. Digital Signal Processing

Training and Workshop

Training:
  • One week VC based training on "Spectrum of Electronics & Communication Engineering and Emerging Technologies", From 16/04/2018 to 27/04/2018.
  • One week training on "Advances in VLSI Technology", at LDCE Ahmedabad, From 28/05/2018 to 01/06/2018.
Workshop:
  • Two days workshop of "e-Yantra from IIT Bombay", at AITS, Rajkot, on 20-21 July, 2017.
  • Two days workshop on "Spectrum Sensing Techniques", GEC Rajkot, on 23-24 February, 2018.

Portfolios

  • Committee Member of MYSY Help Center
  • Committee Member of student chapter
  • Hostel Committee Member
  • Committee Member of student technical event
  • Committee Member of SSIP workshop and seminar

Research Projects

None

Publications

  1. Punit A. Lathiya, Mihir V. Shah, B. Sarvanakumar, Nilesh M. Desai, “Digital Matched Filter Based On-board Radar Signal Processing” ,  International Conference on Electronics and Electrical Engineering (ICEEE)” , pg-40-44, May-2012, ISBN-978-93-81693-93-3
  2. Shyam A. Pankhaniya, Punit A. Lathiya, “A Literature Review on Memory-less Pipeline Dynamic Design Technique”,  Immaculate-2012, A National Level technical symposium held at Gardi Vidyapith , Feb-2012
  3. Nishant Chhatrola, Punit A. Lathiya, “An Efficient Face Recognition Using Principle Component Analysis” , Coimbatore Institute of Information Technology (CiiT) International Journal of Digital Image Processing, Impact Factor-1.76,  June-2014, volume-6, Print: ISSN 0974 – 9691 & Online: ISSN 0974 – 9586
  4. Shital Gondaliya, Punit A. Lathiya, “Ubiquitous Advance Automation” , International Journal of Engineering Development and Research-2014,  ISSN: 2321-9939, March-2014, Impact Factor : 1.79
  5. Dhaivat Vasoya, Punit A. Lathiya, “High Speed and Low power carry select adder design using 180nm Technology”, International Journal of Scientific Research and Development-2014, April: 1.26, ISSN (online): 2321-0613
  6. Rekha T. Vaghela, Punit A. Lathiya, “Comparison and Analysis of Different types of low power techniques with drdaal(Dual Rail Domino with Asynchronounous Adiabatic Logic) Full Adder”,  International Journal of Engineering Rearch and Technology (IJERT), April-2014, vol-3 issue-4
  7. Vipul Kiyada, Punit Lathiya, “High Speed Multiplier Based On Ancient Indian Vedic Mathematics”, International Journal for Scientific Research & Development (IJSRD), June-2015, ISSN (online): 2321-0613
  8. Chaitali Vataliya, Punit A. Lathiya, “Performance Comparison of Carry Save Adder at 180nm, 90nm and 45nm CMOS Technology” , International Journal of Advance Research in Computer Engineering and Technology (IJARCET), volume-5, issue-5, May-2016, ISSN: 2278-1323
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Academic Projects

During the Academic Carrier following projects has been done:

  • B.E. Final Year Project : "Robotics Application Using VLSI"
  • M.E. Dissertation : "Digital Matched Filter ASIC Design for RADAR Signal Processing" at SAC-ISRO,Ahmedabad

Patent Filled

Not Yet Filled any Patent

Professional and Institutional Memberships

ISTE Membership

Expert Lectures

  1. "Modern Digital Design using VHDL" at GEC Patan on 21/2/2014
  2. "VLSI System and Design" at S.R. Patel Engineering College, Unjha on 14/3/2015
  3. "Zigbee Communication and Interfacing" at GEC Rajkot on 7/8/2015 to 8/8/2015.

Awards

  • CLAD (Certified LabVIEW Associate Developer) Certified From National Instrument.
  • Branch Topper in M.E. (Signal Processing and VLSI Technology).
  • Ranked 1 st at “INNOVATE - 2007” – an all India Engineering Design Competition in VLSI, jointly conducted by ALTERA, SLS and BITS - Pilani. (Prize: 4 Laptops)
  • Ranked 1 st at “Vibration-2007” – A National level technical project presentation competition held at V.V.P. engineering College, Rajkot.
  • Ranked 1 st at “Vibration-2007” – A National level robotic competition held at V.V.P. engineering College, Rajkot.
  • Ranked 3 rd at “RESONANCE-2006” – A National level robotic competition held at DDIT, Nadiad.