Mr. RAJESH THAKKER

Faculty Details


  • Designation : Principal
  • Qualification : M. Tech. (Specialization: VLSI) PhD (Specialization: VLSI)
  • Experience : 26 Years
  • Area Of Interest : VLSI, Image Processing

Education Qualification

  • B.E. (Electronics) with Distinction (76 %) from Gujarat University in July 1993. 
  • M.Tech (Microelectronics/VLSI) with CPI of 9.21 from IIT Bombay in January 2002. 
  • PhD (Microelectronics/VLSI) from IIT –Bombay in August 2009.

Work Experience

Sr. No.

Institute Name

Designation

Duration

1.

Shantilal Shah Engineering College – Sidsar, Bhavnagar

Lecturer in EC

(Re-designated Assistant Professor by AICTE in 6th pay scale)

09/11/94 to 07/03/95

2.

Government Engineering College – Modasa

Lecturer in EC (Re-designated Assistant Professor by AICTE in 6th pay scale)

08/03/95 to 06/06/2002

3.

Vishwakarma Government Engineering College – Chandkheda

Lecturer in EC (Re-designated Assistant Professor by AICTE in 6th pay scale)

07/06/2002 to 03/09/2004

4.

Vishwakarma Government Engineering College – Chandkheda

Assistant Professor in EC (Re-designated Associate Professor by AICTE in 6th pay scale)

04/09/2004 to 29/09/2012

5.

Government Engineering College – Bhavnagar

Assistant Professor in EC (Re-designated Associate Professor by AICTE in 6th pay scale)

 

 

30/09/2012 to 25/10/2013

6.

Vishwakarma Government Engineering College – Chandkheda

Professor in EC

26/10/2013 to continue

Skills and Knowledge

Software skills: Programming Languages: 'C', 'C++' Subjects of Expertise: VLSI and Image Processing

Courses Taught

  1. VLSI Technology and Design 
  2. Image Processing 
  3. Physics of MOS Transistor 
  4. CMOS Circuit Design - I 
  5. CMOS Circuit Design - II 
  6. VLSI Test Principles and Architectures 
  7. Low Power CMOS Circuit 
  8. Design Testing and Verification

Training and Workshops

  1. PROBABILITY, RANDOM PROCESSES AND ELEMENTS OF INFORMATION THEORY, IIT KANPUR, QIP, 14-6-1999 to 26-6-1999.
  2. RECENT TRENDS OF UP/PC APPLICATIONS IN ELECTRICAL SYSTEMS, BVM V V NAGAR, ISTE, 25-10-1999 to 6-11-1999.
  3. INTERNET, INTRANET & PROGRAMMING, KREC SURATHKAL, ISTE, 22-11-1999 to 4-12-1999.
  4. BIO-MEDICAL ENGINEERING, NIRMA INSTITUTE OF TECHNOLOGY, AHMEDABAD, ISTE, 8-5-2000 to 20-5-2000
  5. SIGNAL COMPRESSION AND ERROR RESILIENCE, NIRMA INSTITUTE OF TECHNOLOGY, AHMEDABAD, ISTE, 17-11-2003 to 28-11-2003.
  6. DIGITAL IMAGE PROCESSING FOR REMOTE SENSING, IIT BOMBAY, QIP, 8-12-2003 to12-12-2003.
  7. TRAINING OF TRAINER ON NBA ACCREDITATION, CBCS & API, NITTTR EXTENSION CENTRE, AHMEDABAD, 15-7-2013 to 19-7-2013.
  8. DEVELOPING PEOS AND POS IN ELECTRICAL AND ALLIED BRANCHES, NITTTR EXTENSION CENTRE, AHMEDABAD, 2-9-2013 to 6-9-2013.
  9. Industry Academia Collaboration, CoE Pune, 2013-06-13 TO 2013-06-14.
  10. Emerging Research Rends in Computational Intelligence: Theory and Applications, DAIICT – Gandhinagar, 2016-03-01 TO 2016-03-05
  11. Applications of Space Technology in Managing and Monitoring of Risks, GIDM Gandhinagar, 2017-06-24 TO 2017-06-26
  12. Introduction to Robotics, IITRAM – Ahmedabad, 2016-11-18 TO 2016-11-19
  13. Office Adminsitration, SPIPA, Ahmedabad, 2016-02-16 TO 2016-02-20
  14. Disciplinery Appeal & Conduct Rules, SPIPA, Gandhinagar, 2015-07-20 TO 2015-07-22
  15. Education Leadership Development Programme , AICTE, UKIERI - III, New Delhi, 2017-06-28 TO 2017-06-30
  16. Education Leadership Development Programme , AICTE, UKIERI - III, CV Raman Engg. College – Bhubneswar, CV Raman Engg. College – Bhubneswar, 2017-07-31 TO 2017-08-02
  17. Education Leadership Development Programme , AICTE, UKIERI - III, Swami Keshvanand Institute of Technology, Management & Gramothan, Ramngaria, Jagatpura, Jaipur (Rajasthan), 2017-10-04 TO 2017-10-07
  18. Education Leadership Development Programme , AICTE, UKIERI - III, SP College of Engineering, Mumbai, Bhavan’s Campus, Munshi Nagar, Andheri (West), Mumbai – 400058, 2018-01-12 TO 2018-01-14.








Portfolios

  • Academic Section Head at VGEC
  • NBA Coordinator
  • Head of EC Department

Research Projects

Under SSIP: 
  1. Drone Based Imaging System Waste Assessment 
  2. GPS/NavIC Receiver based Pollution Parameters Monitoring System
  3. GPS Based Automatic Speed Control for Accident Prevention 
  4. Automatic Garbage Detection and Collection System

Paper Publication

International Journals:

  1. R. A. Thakker, M. B. Patil, and K. G. Anil, “Parameter Extraction for PSP MOSFET Model using Hierarchical Particle Swarm Optimization,” Elsevier Journal on Engineering Applications of Artificial Intelligence, DOI: 10.1016/j.engappai.2008.07.001, pp. 317-328, Mar. 2009.
  2.  R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. Ramgopal Rao, M. B. Patil, “A Novel Table-based approach for Design of FinFET Circuits ,” IEEE Transactions on CAD, pp. 1061-1070, July 2009.
  3. V. Hariharan, R. Thakker, K. Singh, A. B. Sachid, M. B. Patil, J. Vasi and V. Ramgopal Rao, “Drain Current Model for Nanoscale Double-Gate MOSFETs”, Solid State Electronics (Elsevier), Volume 53, Issue 9, pp. 1001-1008, September 2009.
  4. R. A. Thakker, Maryam B. Shojaei, M. B. Patil, “Automatic Design of Low- power Low-Voltage Analog Circuits using Particle Swarm Optimization with Re-initialization”, Journal of Low Power Electronics 5, American Scientific Publishers, 291–302 (October 2009)
  5. R. A. Thakker, C. Sathe, M. Shojaei Baghini, M. B. Patil, “A Table-based Approach to Study the Impact of Process Variations on FinFET Circuit Performance” IEEE Transactions on CAD, pp. 627-631, Vol. 29, April 2010.
  6. Rajesh A. Thakker, Mayank Srivastava, Ketankumar H. Tailor, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, Mahesh B. Patil, “A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs," Microelectronics Journal, DOI: 10.1016/j.mejo.2011.01.010, May 2011.
  7. Chirag Sheth, Rajesh Thakker, “Performance Evaluation and Comparison of Network Firewalls Under DDoS Attack,” International Journal of Computer Network and Information Security (IJCNIS), ISSN: 2074-9090 (Print), ISSN: 2074-9104 (Online), DOI: 10.5815/ijcnis.2013.12.08, 12, 60-67, October - 2013, MECS Publisher.
  8. Chirag Sheth, Rajesh Thakker, “Performance Optimization of Network Firewalls by Rulebase Reordering based on Traffic Conditions,” Vol. 2, No. 2, pp. 1 – 11, International journal of Computer Science & Network Solutions, Feb. – 2014, Journal ISSN : 2345-3397.
  9. Shilesh Panchal, Rajesh Thakker, “Implementation and Comparative Quantitative Assessment of Different Multispectral Image Pansharpening Approaches”, Int. Journal on Signal and Image Processing, No. 5, Vol. 6, pp. 35-48, October – 2015.
  10. Sarman K. Hadia, R.A. Thakker and Kirit R. Bhatt, “Implementation and comparative analysis of the optimisations produced by evolutionary algorithms for the parameter extraction of PSP MOSFET model”, DOI:10.1080/00207217.2015.1067843, International Journal of Electronics, 07 Sep 2015, Taylor & Francis.
  11. Subhash Patel, Rajesh A Thakker, “Automatic Circuit Design and Optimization Using Modified PSO Algorithm,” JOURNAL OF Engineering Science and Technology Review, 9 (1) (2016) 89-94, ISSN: 1791-2377 © 2016Eastern Macedonia and Thrace Institute of Technology.
  12. Shilesh Panchal, Rajesh Thakker, “Improved Image Pansharpening Technique using Nonsubsampled Contourlet Transform with Sparse Representation,” Journal of the Indian Society of Remote Sensing, July 2016, pp 1-10, Online ISSN: 0974-3006, Springer India.
  13. Shilesh Panchal, Rajesh Thakker, “Contourlet Transform with Sparse Representation-Based Integrated Approach for Image Pansharpening” Journal IETE Journal of Research, Pages 1-11, May 2017.
  14. Mitesh Limachia, Rajesh A. Thakker and Nikhil Kothari, “A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology,” Elsevier Integration, the VLSI Journal, Available online 8 December 2017.
  15. Mitesh Limachia, Dixit Vyas, Rajesh Thakker, Nikhil Kotharia, “Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology” Accepted for publication in Elsevier Integration, the VLSI Journal, March 2018.
  16. Amit Rathod, Rajesh A. Thakker, “Parameter extraction of PSP MOSFET model using Particle Swarm Optimization,” Int. J. Computer Aided Engineering and Technology Vol. X, No. Y,  Inderscience Enterprises Ltd, accepted for publication August, 2017.
  17. Mitesh Limachia, Rajesh A. Thakker and Nikhil Kothari, “Characterization of a Novel 10T SRAM Cell with Improved Data Stability and Delay Performance for 20-nm Tri-Gated FinFET Technology,” ISSN: 0305-6120, Circuit World (Emrald Insight).
  18. Subhash Patel, Rajesh A Thakker, “Analog Circuit Design Using Enhanced Bee Colony Algorithm" is accepted in Journal of Circuits, Systems, and Computers, September – 2018, ISSN (print): 0218-1266 | ISSN (online): 1793-6454, World Scientific. 

International Conferences:

  1. D. Vinay Kumar, R. A. Thakker, M. B. Patil, and V. R. Rao, “Simulation study of non quasi-static behavior of MOS Transistors,”  5th Int. Conf. Modeling and Simulation of Microsystems: Workshop on compact modeling, San Juan, Puerto Rico, pp. 742-745, April – 2002. ISBN No.: 0-9708275-7-1
  2. R. A. Thakker and M. B. Patil, “Hierarchical particle swarm optimization with genetic operations and intensive local search,” Proc. of Int. Conf. on Advances in Control and Optimization of Dynamical Systems, pp. 230-237, Feb. 2007.
  3. A. M. Chopde, S. Khandelwal, R. A. Thakker, S. S. Mande, and M. B. Patil, “Verification of Parameter Extraction Strategy for MOS model 11,” Proc. Int. Conf. on Trends in Intelligent Electronic Systems, pp. 638-642, Nov. 2007.
  4. [R. A. Thakker, N. Gandhi, M. B. Patil, and K. G. Anil, “Parameter extraction for PSP MOSFET model using particle swarm optimization,” Proc. Int. Workshop Phy. of Semi. Dev., pp. 130-133, Dec. 2007. ISBN: 978-1-4244-1728-5
  5. [A. M. Chopde, S. Khandelwal, R. A. Thakker, M. B. Patil, and Anil K. G., “Parameter extraction for MOS model 11 using particle swarm optimization,” Proc. Int. Workshop Phy. of Semi. Dev., pp. 253-256, Dec. 2007. ISBN: 978-1-4244-1728-5
  6. R. A. Thakker, M. B. Patil, and K. G. Anil, “Parameter extraction for Advanced MOSFET model using particle swarm optimization,” Workshop on Compact Modeling, NanoTech -2008, Boston, pp. 845-848, Vol. 3,  June 2008. ISBN: 978-1-4200-8505-1
  7. V. Hariharan, R. A. Thakker, J. Vasi, V. Ramgopal Rao, and M. B. Patil, “Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field Dependent Mobility,” Workshop on Compact Modeling, NanoTech -2008, Boston, pp. 857-860, Vol. 3,  June 2008. ISBN: 978-1-4200-8505-1
  8. A. B. Sachid, M. Srivastava, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, M.B.Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, 20-22 Oct 2008, Taipei, Taiwan (received the best research paper award)
  9. R. A. Thakker, M. Shojaei Baghini, M. B. Patil, “Low-Power Low-Voltage Analog Circuit Design using HPSO”, will be presented in IEEE Int. Conf. on VLSI Design 2009 (Sister Conf. of DAC), pp. 427-432, India, Jan. 2009. ISBN: 978-0-7695-3506-7
  10. Rajesh A. Thakker, Chaitanya Sathe, Angada B. Sachid,  Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil, "A tool for automatic design of FinFET-based circuits," EDA Design Contest at the 22nd International Conference on VLSI Design, January 5-9, 2009.
  11. [R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. Ramgopal Rao, M. B. Patil, “Automated Design and Optimization of Circuits in Emerging Technologies”, IEEE ASP-DAC 2009 (Sister Conf. of DAC), pp. 504-509, Japan, Jan. 2009. ISBN: 978-1-4244-2748-2
  12. [R. R. Navan, R. A. Thakker, S. P. Tiwari, M. Shojaei Baghini, M. B. Patil, S. G. Mhaisalkar, and V. Ramgopal Rao, “DC & transient circuit simulation Methodologies for organic electronics,” in proceeding of 2nd  Int. workshop on Electron Devices and Semiconductor, June 2009. ISBN: 978-1-4244-3831-0
  13. A. B. Sachid, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, V. R. Rao, M. B. Patil, “Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework,” Proc. of 11th  Int. Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA, 22-24 March – 2010. ISBN: 978-1-4244-6454-8
  14.  R. A. Thakker, S. B. Prajapati, M. B. Patil, “Particle Swarm Optimization with Memory Loss Operation,” accepted for publication in 2nd Int. Conf. on Computing, Communication and Networking Technologies (ICCCN), Tamilnadu, to be presented in July-2010.
  15.  S. Prajapati, Niranjan Devashrayee, R. A. Thakker, M. Shojaei Baghini, M. B. Patil, “Performance Evaluation of FinFET and Planar MOSFET Devices at Circuit Level for 45nm Technology,” IEEE/VSI VDAT Symposium 2010, India, July-2010.
  16. [Chirag Sheth, R. A. Thakker, “Performance Evaluation and Comparative Analysis of Network Firewalls,” accepted for publication Int. Conf. on Devices and Communication, Feb. 2011, BITs, Mesra, India, ISBN No. 978-1-4244-9189-6
  17. Ravi C. Butani, Bhavin D. Gajjar, Rajesh A. Thakker, “Performance evaluation of Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) Algorithm,” International Conference on Advanced Computing, Communication and Networks’11, pp. 108-112, June – 2011.
  18. Kalpesh C. Chheladiya, Paresh N. Chavada [IEEE Student Member], Rajesh A. Thakker, “Switch-based Reconfigurable Photovoltaic Array for Power Maximization,” Poster Category in International Conference on Emerging Electronics (ICEE), December – 2012.
  19. Amit C. Rathod, Rajesh A. Thakker, “FPGA Realization of Particle Swarm Optimization Algorithm with Floating Point Arithmetic,” IEEE international conference on High performance computing and applications at Bhubaneswar, December 2014.
  20. Rachana A Patel, Rajesh A. Thakker, “Review of Contemporary Research in FinFET Technology,” International Conference on Advances in Engineering 22nd – 23rd  January 2015, Mehsana, Gujarat, India
  21. Jitendra B. Chinchore, Rajesh A. Thakker, “Design of Low Dropout Regulator Using Artificial Bee Colony Evolutionary Algorithm,” International Conference on Circuit, Power, Computing Technologies, Kumaracoil on the 19th - 20th of March 2015.
  22. Chirag Sheth, R. A. Thakker, “Scalable Design of Open Source based Dynamic Routed Network for Interconnection of Firewalls at Multiple Geographic Locations”,  International Conference on ICT for Intelligent Systems (ICTIS – 2015), Ahmedabad.
  23. Mitesh Limachhia, Rajesh Thakker, and Nikhil Kothari, “Analysis of FinFET based SRAM Cell Stability under Work Function Variability,” 7th IEEE International Workshop on Reliability Aware System Design and Test 2016 (Jointly with 29th Int. Conf. on VLSI Design), Kolkata, Jan – 2016.
  24. K.R.Trivedi, R. A. Thakker, “'Brainwave Enabled Multifunctional, Communication, Controlling and Speech Signal Generating System,” International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016, Chennai, Tamil Nadu, 3-5 March, 2016.
  25. Bhavesh Soni, Gaurav Aryan, Ronit Solanky, Adit Patel, Rajesh A Thakker, “Performance Evaluation of 14 nm FinFET based Ring Counter using BSIM-CMG Model” 5th International Conference on Innovations in Electronics and Communication Engineering (ICIECE - 2016), Hyderabad, India, July – 2016.
  26. Mitesh Limachia, Pathik Viramgama, Dr. Rajesh Thakker and Dr. Nikhil Kothari, “Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin,” 30th VLSI Design Conference held in Hyderabad, India, 7th – 11th Jan – 2017.
  27. Kishankumar Suthar and Rajesh Thakker, A New Global Shutter 8T CIS Architecture with CDS Operation, Proceedings of the International Conference on Intelligent Systems and Signal Processing (ISSP-2017), Advances in Intelligent Systems and Computing, pp. 113-124, May – 2017.
  28. Subhash Patel, Rajesh A. Thakker, “Parasitic Aware Automatic Analog CMOS Circuit Design Environment using ABC Algorithm,” 31st Int. Conf. on VLSI Design, Pune, Jan – 2018.
  29. Amit Rathod, Rajesh A. Thakker, "Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization – SoC Approach" accepted at 22nd VLSI Design and Test Symposium (VDAT-2018) to be held at Thiagarajar College of Engineering, Madurai from June 28th to 30th June, 2018.
  30. Subhash Patel, Rajesh A. Thakker, "Parasitic-Aware Automatic Analog CMOS Circuit Design Environment" is selected under full paper category at VLSID-2019 conference.

National Conference Papers:
  1. Hetal Bhatt, Rajesh A. Thakker, “MATLAB-based Simulation of Photovoltaic Solar Cell and its Array at Different Temperature Values,” National Conference on Recent Trends in Engineering and Technology, May – 2011, Vallabh Vidyanagar.
  2. Anand Patel, R. A. Thakker, “Medical Signal and Image Processing using Wavelet Transform,” SPCE National Conference, Feb – 2012.
  3. Hetal Bhatt, Rajesh A. Thakker, “DEVELOPMENT OF PHOTOVOLTAIC MODEL FOR SOLAR CELL AND ARRAY FOR DIFFERENT TEMPERATURE ENVIRONMENT AND VALUES OF SERIES RESISTANCE USING MATLAB, SPCE National Conference, Feb – 2012.
  4. Rohit B. Vasoliya, Rajesh Thakker, SatyajitMohapatra, Nihar R. Mohapatra, Harishanker Gupta Digital Background Calibration using CFCS Technique for 3.5bits/stage 16-bit Pipelined ADC, NCERTE, 4th to 6th April – 2016, Chandkheda, Ahmedabad.
  5. Rushabh Kothari, Darshana Mistry and Rajesh Thakker, Defect Detection in Smooth and Rough Surface of Plain Color Tile, NCERTE, 4th to 6th April – 2016, Chandkheda, Ahmedabad.

Monograph/Book Published:

Rajesh A. Thakker, Mahesh B. Patil, Maryam Baghini Shojaei, “Applications Evolutionary Algorithms in VLSI,” LAP LAMBERT Academic Publishing GmbH & Co. KG, ISBN 978-3-8454-0434-9, August/September - 2011

Academic Projects

  • Contributed in Institute Manual Degree Engineering
  • Revision of Syllabus of BE and ME (BoS Member)

Patents Filed

US Patent

Rajesh Thakker, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate" Patent No.: US 8,089,314 B2, Date of Issue: Jan. 3, 2012

European Patent:

Rajesh Thakker, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “OPERATIONAL AMPLIFIER HAVING IMPROVED SLEW RATE,” European Patent Application EP2543141, Publication Date: Jul 9, 2014

Indian Patent filed:

 1.      Kiran Trivedi and Rajesh A. Thakker, Title of invention - – “Brainwave enabled multifunctional, communication, controlling and speech signal generating device,” Indian patent submitted on 01/01/2013, Publication Date : 17/10/2014

 2.      Chirag Sheth, Rajesh Thakker, System and Method for Interconnection of Firewalls at multiple geographic locations through a Standalone Network, 384/MUM/2015, 5th February, 2015.

 3.      Priyank V. Virani, Nainesh P. Makwana, Suraj B. Sarvaiya, Prakash N. Solanki, Rajesh A. Thakker, and Chirag Sheth “ Low Cost, Wi-Fi Router and Mobile Handset based Intercom System” Filed in May – 2016.

 4.      Mitesh Limachia, Rajesh A. Thakker, Nikhil Kothari, “A Near-Threshold 10T SRAM Cell With High Read and Write Margins for Tri-Gated FinFET Technology” Filed in September – 2016.

 5.      Mitesh Limachia, Rajesh A. Thakker, Nikhil Kothari, “Hybrid Offset Compensated Latch Type Sense Amplifier (HOCLSA) for Ti-Gated FinFET Technology,” Filed on 22/12/2016.

Professional Institution Membership

ISTE Life Member

Workshop/Seminar/Expert Talk/Awards

  1. Session chair in Signal and Image Processing track, INDICON 2009 (19 Dec, 2009).
  2. “Automatic Circuit Design for Emerging Technology”, 4th  National Conference on Current Trends in Technology–NUCONE Nov. 2009 (26th November 2009).
  3. “Automatic Circuit Design for Emerging Technology”, STTP on Recent Trends in Embedded Systems, VLSI Designing and Power Electronics, October – 2011 (16th October, 2011), Parul Institute of Engineering & Technology, Waghodia, Dist. Vadodara.
  4. “Organic Electronics” 2nd International Conference on Current Trends in Technology, NUiCONE 2011 (15/11/2011)
  5. “Design of Circuits in FinFET Technology”, STTP Embedded System Design, R. K. University – Rajkot, Dec – 2011 (22/12/2011)
  6. “Organic Electronics and RFID” National Conference on Technology and Management – 2012 (Jan.) at SPCE – Visnagar. 21/01/2012
  7. Session chair in Electronic track at National Conference on Technology and Management – 2012 (Jan.) at SPCE – Visnagar. 21/01/2012
  8. Delivered expert talk on “Interfacing Memory and Programming I/O Ports for Microcontroller – 8051” during Five days (29th October to 2nd November 1, 2012) STTP on "Microcontrollers and Embedded Systems" arranged by NITTTR Bhopal's Extension Centre at Sola, Ahmedabad.  30th October 2012
  9. Delivered expert talk on “Design of Circuits in FinFET Technology” at Parul Institute of Engineering and Technology, Vadodara during National Seminar on Recent Trends in VLSI on January 17, 2014.
  10. Delivered expert talk on “Design of Circuits in FinFET Technology” at RTEECE – 2014 Conference at ITM University on January 17, 2014.
  11. Delivered expert talk on “Design of Circuits in FinFET Technology” at GTU – Ahmedabad during research week on March 22, 2014.
  12. Delivered expert talk on “Low Power CMOS Circuit Design” at Charusat, EC Department on April 12, 2014.
  13. Delivered expert talk on “VLSI Design and Technology” at S. P. B. Patel Engineering College (Saffrony) on April 23, 2014.
  14. Delivered expert talk on “FinFET” on 06/01/2015 during three days (5th January to 7th January - 2015) in STTP on "An Intellectual Insight on Analog and Digital VLSI Design " arranged by GEC - Gandhinagar.
  15. Session chair in 1st International conference on “Advances in Engineering” on 23rd  January, 2015 at Saffrony Institute of Technology, Mehsana.
  16. Session chair in 2015, 19th International Symposium on VLSI Design and Test (VDAT)  "EDA, Algorithm and Emerging Trends."
  17. VDAT-2015 Organizing Committee Member, Education Day Chairs.
  18. Chief Guest and Speaker (Introduction to EDA Tools and Applications, STTP  on 'Electronic Design Automation Tools' organized by Electronics Department, 4th January -2016.
  19. Coordinator for National Conference on Emerging Research Trends in Engineering – 2016, VGEC – Chandkheda, 4th to 6th April – 2016.
  20. Expert Talk on FinFET Fundamentals , STTP on "VLSI and Embedded System Design," Nirma University, Ahmedabad, 2nd July – 2016.
  21. Expert Talk on Low Power CMOS VLSI Design, Two Days Workshop on “Research Opportunities in VLSI”, GEC – Bhavnagar, 23rd August – 2016
  22. Expert Talk on CMOS PLL Design, One Week STTP on “RF and Microwave Communication Engineering”, LDCE - Ahmedabad, 23rd November – 2016.
  23. Expert Talk on Parameter Extraction of Advanced Models using Evolutionary Algorithms, SAMVAAD – 2017 at Silver Oak Institute of Technology, Ahmedabad, 22nd December – 2017.
  24. Session Chair, GUJCOST & DST Sponsored Two days International Conference on “Advances in Engineering &Technology” (AIET-2018) during 9-10 July 2018, Silver Oak College of Engineering & Technology

Awards

  1. A. B. Sachid, M. Srivastava, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, M.B.Patil, V. Ramgopal Rao, “Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies”, Intel Asia Academic Forum 2008, 20-22 Oct 2008, Taipei, Taiwan (received the best research paper award)  
  2. CMI Level 5 Certificate awarded by UKIERI-IAICTE 
  3. US Patent Granted: Rajesh Thakker, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, “Operational Amplifier Having Improved Slew Rate" Patent No.: US 8,089,314 B2, Date of Issue: Jan. 3, 2012